1. Field of the Invention
The present invention relates to the formation of metal interconnections on semiconductor wafers. More particularly, the present invention relates to the formation of dual damascene interconnects with improved electro migration lifetimes.
2. Description of the Related Art
As integrated circuit devices grow smaller and smaller, higher conductance and lower capacitance is required of the interconnects. In order to accommodate these objectives, the trend has been towards the use of copper for interconnects and damascene methods for forming the interconnects. One drawback to the use of copper in the interconnects and metallization conductor is its tendency to diffuse (i.e., leakage) into adjacent dielectric layers. Copper diffuses easily into dielectric layers and diminishes the electrical insulation qualities of the dielectric.
Copper barrier layers, for example layers containing tantalum, have been deposited before the deposition of copper to prevent “leakage”. This barrier layer must be able to prevent diffusion, exhibit low film resistivity, have good adhesion to dielectric and Cu and must also be CMP compatible. Also the layer must be conformal and continuous to fully encapsulate Cu lines with as thin a layer as possible. Due to higher resistivity of barrier material, the thickness should be minimized for Cu to occupy the maximum cross-sectional area.
Failures due to electromigration are also major reliability concern for the use of copper in forming interconnects. Electromigration is the current induced diffusion of atoms due to the momentum transfer from moving atoms. Electromigration may result in voiding and thus open circuit failures. Currently, the reliability of copper interconnects, i.e., the electro-migration lifetimes of CU-dual damascene interconnects, are limited by voids formed at the top-via to bottom metal interface. These voids are typically caused by electromigration and stress migration. Although such voids may be present at various portions of the conductive metal lines, when these voids coincide with the via—bottom metal interface, the via connection fails or becomes highly resistive. That is, the presence of such voids make the multi-level metallization layers vulnerable to failure by producing open circuits at the interface where one metal level contacts another. These voids are influenced by a number of factors including the barrier layers, seed layer quality, copper fill, thermal processing history and CMP performance.
Current approaches to these interface void problems include using multiple contacts to increase the electro migration lifetime from 50% to 100%. For example, second and third redundant vias are added. But this method requires more area for layouts. Moreover, stacked vias may not be permitted if the design tool rules are enforced. An alternative approach adds top shunts to the copper wiring. That is, a shallow layer of a second conductive material is added. But this adds extra processing steps and feasible manufacturing processes to incorporate these steps have not yet been developed. Yet another alternative approach involves alloying the copper. For this approach a suitable alloy that meets the electro migration objectives without severely impacting the copper wire bulk resistance has yet to be found.
Accordingly, what is needed is better methods and structures for forming top-via to bottom metal contacts in such a manner as to avoid electro migration problems.